MIPI interface

I. MIPI MIPI (Mobile Industry Processor Interface) is an acronym for Mobile Industry Processor Interface.
MIPI (Mobile Industry Processor Interface) is an open standard for mobile application processors initiated by the MIPI Alliance.

The specifications that have been completed and are in the plan are as follows: Write a picture description here
SECOND, MIPI ALLIANCE’S MIPI DSI SPECIFICATION
1, noun interpretation
The CS of the DCS (DisplayCommandSet) is a standardized set of commands for display modules in command mode.
DSI, CSI (DisplaySerialDisplay, CameraSerialInterface)
DSI defines a high-speed serial interface between the processor and the display module.
CSI defines a high-speed serial interface between the processor and the camera module.
D-PHY: Provides physical layer definitions for DSI and CSI
2, DSI layered structure
DSI is divided into four layers, corresponding to D-PHY, DSI, DCS specification, hierarchical structure diagram as follows:
PHY defines the transmission medium, the input/output circuit, and the clock and signal mechanism.
Lane Management Layer: Send and collect data flow to each lane.
Low Level Protocol layer: Defines how frames and resolutions are framed, error detection, and so on.
Application layer: Describes high-level encoding and parsing data flows.

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3, Command and Video Mode
DSI-compatible peripherals support Command or Video operating modes, which mode is determined by the peripheral architecture Command mode refers to sending commands and data to a controller with a display cache. The host indirectly controls the peripheral through commands.
Command mode uses two-way interface Video mode refers to the use of real-image streams from the host to the peripheral. This mode can only be transmitted at high speeds.

To reduce complexity and save costs, video-only systems may have only one one-way data path
Introduction to D-PHY
1, D-PHY describes a synchronous, high-speed, low-power, low-cost PHY.
A PHY configuration includes
A clock lane
One or more data lane
The PHY configuration for two Lanes is shown below
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Three main lane types
One-way clock Lane
One-way data Lane
Two-way data Lane
D-PHY transmission mode
Low-power (Low-Power) signal mode (for control): 10MHz (max)
High-speed signal mode (for high-speed data transmission): 80Mbps to 1Gbps/Lane
The D-PHY low-level protocol specifies that the minimum unit of data is a byte
When sending data, it must be low in front and high in the back.
D-PHY for mobile applications
DSI: Display serial interface
One clock lane, one or more data lane
CSI: Camera Serial Interface
2, Lane module
PHY consists of D-PHY (Lane Module)
D-PHY may contain:
Low-power transmitter (LP-TX)
Low-power receiver (LP-RX)
High-speed transmitter (HS-TX)
High-speed receiver (HS-RX)
Low-power Competitive Detector (LP-CD)
Three main lane types
One-way clock Lane
Master: HS-TX, LP-TX
Slave: HS-RX, LP-RX
One-way data Lane
Master: HS-TX, LP-TX
Slave: HS-RX, LP-RX
Two-way data Lane
Master, Slave: HS-TX, LP-TX, HS-RX, LP-RX, LP-CD
3, Lane state and voltage
Lane State
LP-00, LP-01, LP-10, LP-11 (single-ended)
HS-0, HS-1 (difference)
Lane voltage (typical)
LP: 0-1.2V
HS: 100-300mV (200mV)
4, operating mode
Three operating modes for Data Lane
Escape mode, High-Speed mode, Control mode
Possible events from the stop state of control mode are:
Escape mode request (LP-11-LP-10-LP-00-LP-01-LP-00)
High-Speed mode request (LP-11-LP-01-LP-00)
Turnaround request (LP-11-LP-10-LP-00-LP-10-LP-00)
Escape mode is a special operation of data Lane in the LP state
In this mode, you can enter some additional functions: LPDT, ULPS, Trigger
Data Lane enters Escape mode via LP-11- LP-10-LP-00-LP-01-LP-00
Once in Escape mode mode, the sender must send 1 8-bit command in response to the requested action
Escape mode uses Spaced-One-Encoding Hot
Ultra-Low Power State
In this state, lines are empty (LP-00)
The ultra-low power state of Clock Lane
Clock Lane enters ULPS state via LP-11-LP-10-LP-00
- Exit this state via LP-10 , TWAKEUP , LP-11, minimum TWAKEUP time is 1ms
High-speed data transmission
The act of sending high-speed serial data is called high-speed data transfer or triggering (burst)
All Lanes doors start synchronously and the end time may vary.
The clock should be in high-speed mode
The transfer process under each mode operation
The process of entering Escape mode: LP-11- LP-10- LP-00-LP-01-LP-01-LP-00-Entry Code-LPD (10MHz)
The process of exiting Escape mode: LP-10-LP-11
The process of entering high-speed mode: LP-11- LP-01-LP-00-SoT (00011101) – HSD (80Mbps to 1Gbps)
The process of exiting high-speed mode: EoT-LP-11
Control mode – BTA transmission process: LP-11, LP-10, LP-00, LP-10, LP-00
Control mode – BTA receiving process: LP-00, LP-10, LP-11

State transition diagram

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Introduction to DSI
1, DSI is a Lane extensible interface, 1 clock Lane/1-4 data Lane Lane
DSI-compatible peripherals support 1 or 2 basic modes of operation:
Command Mode (similar to MPU interface)
Video Mode (similar to RGB interface) – Data must be transferred in high-speed mode to support data transfer in 3 formats
Non-Burst Synchronous Pulse Mode
Non-Burst Synchronous Event Mode
Burst mode
Transmission mode:
High-speed signal mode (High-Speed signaling mode)
Low-power signal mode (Low-Power signaling mode) – only data lane 0 (clock is different or come from DP, DN).
Frame type
Short frames: 4 bytes (fixed)
Long frames: 6 to 65541 bytes (variable)
Two examples of high-speed data Lane transmission
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2, short frame structure
Frame head (4 bytes)
Data Identification (DI) 1 byte
Frame data – 2 bytes (length fixed to 2 bytes)
Error Detection (ECC) 1 byte
Frame size
The length is fixed to 4 bytes
3, long frame structure
Frame head (4 bytes)
Data Identification (DI) 1 byte
Data count – 2 bytes (number of data filled)
Error Detection (ECC) 1 byte
Data fill (0 to 65535 bytes)
Length s.WC?bytes
End of frame: checksum (2 bytes)
Frame size:
4 s (0 to 65535) and 2 s 6 to 65541 bytes
4, frame data type Here are the picture descriptions of the five, MIPI DSI signal measurement instance 1, MIPI DSI signal measurement map 2 in Low Power mode, MIPI D-PHY and DSI transmission mode and operation mode . . . D-PHY and DSI transmission mode , low power (Low-Power) signal Mode (for control): 10MHz (max) – High Speed signal mode (for high-speed data transmission): 80Mbps to 1Gbps/Lane – D-PHY mode of operation – Escape mode, High-Speed (Burst) m ode, Control mode , DSI mode of operation , Command Mode (similar to MPU interface) – Video Mode (similar to rGB interface) – Data must be transmitted in high-speed mode 3, small conclusions – Transmission mode and operation mode are different concepts . . . The Transmission mode of High-Speed must be used in Video Mode operating mode. However, command Mode mode is usually used to read and write registers when LCD modules are initialized, because data is not prone to errors and easy to measure at low speeds. Video Mode can also send instructions using High-Speed, and Command Mode can also use High-Speed operating mode, but it’s not necessary to do so.